Lead RTL and microarchitecture development using SystemVerilog and Chisel for SoC/digital subsystems, drive verification and power-aware flows (UPF/CPF, CDC/RDC, GLS, FPGA), integrate mixed-signal IP, support synthesis/P&R/tapeout, apply low-power techniques, adopt AI tools to accelerate design/verification, coordinate cross-functional teams, and mentor junior engineers to deliver complex chip projects on schedule.

Lead end-to-end DFT for wireless SoCs: define DFT architecture, implement scan/MBIST/JTAG solutions, generate and validate ATPG/MBIST patterns, support gate-level simulation and silicon bring-up, drive post-silicon debug, yield analysis, automation, and cross-functional tapeout collaboration.

Lead product vision, strategy and roadmaps for wireless IoT semiconductor products. Drive pricing, datasheets, technical documentation, go-to-market, and cross-functional coordination with engineering, sales, marketing, FAEs and project teams. Prioritize features, manage tradeoffs, perform market research and competitive analysis, and track product performance from concept through launch.