Teams at Goldman Sachs

Design, build, and maintain high-performance FPGA trading platforms and order management workflows. Implement and optimize HDL (SystemVerilog) code, create testbenches and simulations, ensure low-latency interaction with hardware and networks, and collaborate globally through full product lifecycle from requirements to monitoring.

Monitor and control confidential information flows between private and public business lines, maintain restricted/confidential lists, apply research and settlement rules, manage materiality checking and workflow approvals, liaise with Legal and Compliance teams, and support cross-regional enhancement projects.

Design, build, and optimize low-level, high-performance Linux systems (C/C++/Java). Work across kernel and user space on networking, I/O, memory, and scheduling for deterministic low latency. Implement or tune kernel-bypass networking (DPDK/netmap/XDP), profile with perf/eBPF/ftrace, and collaborate on production SLOs, runbooks, and reproducible performance tests.