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Optiver

FPGA Engineer

Posted 3 Days Ago
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Sydney, New South Wales
Senior level
Sydney, New South Wales
Senior level
As a Senior FPGA Engineer, you will develop low latency trading solutions, collaborate with stakeholders, and mentor junior developers, ensuring system quality and performance.
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WHO WE ARE

Optiver is a tech-driven trading firm and leading global market maker. For over 35 years, Optiver has been improving financial markets around the world, making them more transparent and efficient for all participants. With more than 1,600 employees in offices around the world, we’re united in our commitment to improve the market through competitive pricing, execution and thorough risk management. By providing liquidity on multiple exchanges across the world, we actively trade on 70+ exchanges, where we’re trusted to always provide accurate buy and sell pricing – no matter the market conditions. 

Optiver’s Sydney office is one of the primary players within Asian markets, trading a range of products. Established in 1996, we're an active participant on the Hong Kong, Korea, Singapore, Taiwan and Japan exchanges, and act as Optiver’s APAC head office. 


WHAT YOU’LL DO

As a senior FPGA developer, you'll work with internal stakeholders (including trading, risk, compliance and research teams), to develop Optiver's low latency execution and network optimisation platforms. Our execution platforms are responsible for placing orders from auto-trading systems with as low a latency as possible, implementing risk boundary checks, order management and exchange connectivity. You'll get to:

  • Develop solutions for our business challenges by implementing key features in our execution applications, through to testing, deployment and monitoring.
  • Experience the excitement of our fast-paced development cycle – owning a tight feedback loop, testing and shipping your code to production within days.
  • Collaborate with other software developers and contribute to the design and implementation of our high performance software applications.
  • Flex your understanding of FPGA fundamentals by shaving out levels of logic to achieve a zero latency design.

Your key responsibilities will include:

  • Implement and build solutions to enable our low latency trading and help Optiver retain its number one status in the market.
  • Liaise with stakeholders across the company to build the best solutions for Optiver.
  • Manage deployments to reduce risk and provide production support where required.
  • Help ensure quality is maintained throughout our systems, including via code reviews.
  • Contribute to our never-ending goal of continuous improvement, such as by providing feedback on where our systems and controls can be improved.
  • Provide advice and guidance to junior developers.


WHO YOU ARE

To be successful for this role, you'll need to be someone with:

  • 5+ years’ experience in FPGA development.
  • Proficient in one or more of the following: VHDL, Verilog, System Verilog.
  • Experience leading projects as a technical leader. 
  • Basic skills in either C++, C, or Python. 
  • Experience working with Linux.
  • Understanding of computer networks and protocols (TCP, IP, UDP).


WHAT YOU'LL GET

  • The chance to work alongside diverse and intelligent peers in a rewarding environment.
  • Competitive remuneration, including an attractive bonus structure and additional leave entitlements.
  • Training, mentorship, and personal development opportunities.
  • Gym membership plus weekly in-house chair massages.
  • Daily breakfast, lunch, and an in-house barista.
  • Regular social events including an annual company trip.
  • A work-from-home allowance and support.
  • Guided relocation, a competitive relocation package and visa sponsorship where necessary.

As an intentionally flat organisation, we believe that great ideas and impact can come from everyone. We are passionate about empowering individuals and creating diverse teams that thrive. Every person at Optiver should feel included, valued, and respected, because we believe our best work is done together.
Our commitment to diversity and inclusion is hardwired through every stage of our hiring process. We encourage applications from candidates from all backgrounds, and we welcome requests for reasonable adjustments during the process to ensure that you can best demonstrate your abilities.

Top Skills

C
C++
Ip
Linux
Python
System Verilog
Tcp
Udp
Verilog
Vhdl

Optiver Sydney, New South Wales, AUS Office

Sydney, New South Wales, Australia

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