Own IT service delivery end-to-end, drive automation to remove manual toil, build integrations across identity/SSO/device management and cloud, support multi-OS environments and local network/infrastructure, provide hands-on Level 1–4 support, and maintain security/compliance-aligned runbooks and documentation.

Lead end-to-end DFT for wireless SoCs: define DFT architecture, implement scan/MBIST/JTAG solutions, generate and validate ATPG/MBIST patterns, support gate-level simulation and silicon bring-up, drive post-silicon debug, yield analysis, automation, and cross-functional tapeout collaboration.

Lead RTL and microarchitecture development using SystemVerilog and Chisel for SoC/digital subsystems, drive verification and power-aware flows (UPF/CPF, CDC/RDC, GLS, FPGA), integrate mixed-signal IP, support synthesis/P&R/tapeout, apply low-power techniques, adopt AI tools to accelerate design/verification, coordinate cross-functional teams, and mentor junior engineers to deliver complex chip projects on schedule.